1. Field of the Invention:
This invention relates to integrated circuit packaging technology, and more particularly, to a multi-chip module used to pack two or more semiconductor chips in a stacked manner and method of fabricating the same.
2. Description of Related Art:
Multi-chip packaging technology is used to pack two or more semiconductor chips over substrate or leadframe in one single package module, so that one single package module is capable of offering a manifold level of functionality or data storage capacity. Conventionally, there are two schemes to mount two or more chips on a single substrate. One scheme is to mount these chips in a side-by-side manner over the substrate. This scheme allows the resulted multi-chip module to be low in height, but one drawback is that it would require a substrate of a large surface area to implement. During SMT (Surface Mount Technology) process, a larger substrate would be more easily subjected to warpage, resulting in undesired delamination or peeling of the chips from the substrate. The finished product of the multi-chip module would therefore have reliability concern. Another scheme is to mount the chips in a stacked manner. Although this scheme would make the resulted multi-chip module greater in height, it can help to prevent the above-mentioned problem of delamination or peeling due to the use of a large substrate.
FIG. 6 is a schematic diagram showing a conventional stacked type of multi-chip module. As shown, this multi-chip module 1a includes a first chip 10a and a second chip 12a, wherein the first chip 10a is adhered to a substrate 11a and the second chip 12a is mounted over the first chip 10a in a stacked manner. The first chip 10a is electrically connected to the substrate 11a by means of a first set of gold wires 13a, and the second chip 12a is electrically connected to the same by means of a second set of gold wires 14a. One drawback to this multi-chip module, however, is that the second chip 12a should be smaller in size than the first chip 10a due to the reason that part of the surface of the first chip 10a is occupied by the first set of gold wires 13a. This restriction limits the use of this multi-chip module to pack chips of the same size or variably-selected sizes.
One solution to the foregoing problem is disclosed in U.S. Pat. No. 5,793,108, which is illustrated in FIG. 7. This patented multi-chip module 1b is characterized by that it includes two chips 10b, 12b which are mounted in a stacked back-to-back manner over a die pad 110b, wherein the first chip 10b has its active surface adhered to the die pad 110b and electrically connected to the leads 111b by means of a first set of gold wires 13b, and the second chip 12b has its non-active surface adhered to the non-active surface of the first chip 10b and electrically connected to the leads 111b by means of a second set of gold wires 14b. This stacked back-to-back structure allows two chips of the same size to be packed in the same module. One drawback to this multi-chip module, however, is that it would be unsuitable for use to pack two chips of the same functionality due to the reason that it would be difficult to arrange the I/O pads on the two chips for external connections.
Another solution that can pack two or more chips of the same size or variably-selected sizes in the same module is disclosed in U.S. Pat. No. 5,323,060, which is illustrated in FIG. 8. As shown, this patented multi-chip module 1c can be used to pack a plurality of chips, for example four chips 10c, 11c, 12c, 13c, of the same size. These chips 10c, 11c, 12c, 13c are mounted in a stacked manner and adhered to each other by means of adhesive layers 14c. The first chip 10c is electrically connected to the leads 157c by means of a first set of gold wires 16c; the second chip 11c is electrically connected to the same by means of a second set of gold wires 17c; the third chip 12c is electrically connected to the leads 157c by means of a third set of gold wires 18c; and the fourth chip 13c is electrically connected to the leads 157c by means of a fourth set of gold wires 19c. One drawback to this patented multi-chip module, however, is that the adhesive layers 14c should be greater in height than those parts of the gold wires that are positioned above the chips 10c, 11c, 12c, 13c, and smaller in horizontal extent than the chips 10c , 11c, 12c, 13c so that they would not touch the gold wires 16c, 17c, 18c, 19c. This structure allows the chips 10c, 11c, 12c, 13c to be variably sized according to actual needs. This patented multi-chip module, however, has the following drawbacks. First, only the bond pads on the bottommost chip 10c are under-supported, while the bond pads on the overlaid chips 11c, 12c, 13c are suspended without undersupport. Therefore, during wire-bonding process, it would easily cause these overlaid chips 11c, 12c, 13c to be cracked. Second, in the event that the adhesive layers 14c are inadequately dimensioned to the required thickness, it would make the wire-bonding process for the bonding wires 16c, 17c, 18c, 19c to be difficult to carry out. Third, it would make the resulted multi-chip module exceedingly great in height and therefore would not meet compactness requirement. Fourth, due to the existence of the adhesive layers 14c between the chips 10c, 11c, 12c, 13c, there would exist voids between the chips 10c, 11c, 12c, 13c after the multi-chip module is encapsulated through molding process, which would adversely degrade the quality of the resulted multi-chip module.
Still another solution that can pack two or more chips of the same size or variably-selected sizes in the same module is disclosed in U.S. Pat. No. 5,721,452, which is illustrated in FIG. 9. As shown, this patented multi-chip module 1d includes a first chip 10d and a second chip 12d. The first chip 10d has two rows of edge-located bond pads 100d, and the second chip 12d also has two rows of edge-located bond pads 120d. This patented multi-chip module is characterized by that the first chip 10d is stacked in a crossed manner over the second chip 12d, so that the bond pads 100d on the first chip 10d can be separately positioned from the bond pads 120d on the second chip 12d, allowing a first set of gold wires 13d to be connected to the bond pads 100d on the first chip 10d and a second set of gold wires 14d to be connected to the bond pads 120d on the second chip 12d without difficulty. One drawback to this patented multi-chip module, however, is that the bond pads 120d on the overlaid second chip 12d are suspended without undersupport, which would easily cause the second chip 12d to be cracked during the wire-bonding process for the second chip 12d. One solution to this problem is to dispose a pillar (not shown) beneath the bond pads 120d to undersupport the bond pads 120d. One drawback to this solution, however, is that it would make the overall fabrication process more complex and costly to implement. Moreover, by this patented technology, the bond pads 100d on the first chip 10d can only be edge-located but cannot be peripherally-located; and the bond pads 120d on the second chip 12d can only be edge-located but cannot be peripherally- located; otherwise, it would make the wire-bonding process difficult to carry out.
It is therefore an objective of this invention to provide a multi-chip module and method of fabricating the same, which can be used to pack two or more chips of variably-selected sizes in the same module.
It is another objective of this invention to provide a multi-chip module and method of fabricating the same, which can prevent the chips from being cracked during wire-bonding process.
It is still another objective of this invention to provide a multi-chip module and method of fabricating the same, which allows the resulted package size to be low in height.
It is yet another objective of this invention to provide a multi-chip module and method of fabricating the same, which can be used to pack two or more chips of the same functionality in the same package.
It is still yet another objective of this invention to provide a multi-chip module and method of fabricating the same, which can be used to pack two or more chips with variously-located bond pads, including single-sided, double-sided, and peripherally-located bond pads, in the same package.
It is still yet another objective of this invention to provide a multi-chip module and method of fabricating the same, which can prevent the existence of voids in the encapsulation body so as to assure the quality of the resulted package.
In accordance with the foregoing and other objectives, the invention proposes a new multi-chip module and method of fabricating the same.
The multi-chip module of the invention comprises: a chip carrier, at least a first semiconductor chip having an active surface and a non-active surface, with the non-active surface being adhered to the chip carrier; a first set of bonding wires, each having an outer end bonded to the chip carrier and an inner end bonded to the active surface of the first semiconductor chip to electrically connect the first semiconductor chip to the chip carrier; at least a second semiconductor chip having an active surface and a non-active surface; an adhesive layer for adhering the non-active surface of the second semiconductor chip to the active surface of the first semiconductor chip; the adhesive layer being formed to a thickness that allows it to entirely wrap the part of the first set of bonding wires that is positioned above the active surface of the first semiconductor chip to prevent the first set of bonding wires to come in contact with the non-active surface of the second semiconductor chip; a second set of bonding wires, each bonded to the active surface of the second semiconductor chip to electrically connect the second semiconductor chip to the chip carrier; and an encapsulation body for encapsulating the first semiconductor chip, the first set of bonding wires, the second semiconductor chip, and the second set of bonding wires.
To allow the bent portions of the first set of bonding wires to be positioned above the substrate rather than above the first semiconductor chip, a reverse wire-bonding technique is employed, by which the first set of bonding wires are bonded in such a manner that the outer ends thereof are first bonded to the substrate, and then the inner ends thereof are pulled up towards the bond pads of the first semiconductor chip and then stitch bonded to the bond pads. Owing to the reverse wire-bonding, the topmost portion of the first set of bonding wires would be nearly leveled with the top surface of the first semiconductor chip rather than exceedingly above the top surface of the first semiconductor chip.
The substrate can be, for example, a BGA (Ball Grid Array) substrate having a front surface and a back surface, wherein the front surface is used for die mounting and is formed with a plurality of electrically-conductive traces, while the back surface is used for the attachment of an array of solder balls which allows the chips on the front surface to be electrically connected to external circuitry.
In another embodiment, the substrate can be a leadframe having a die pad for die mounting and a plurality of leads for the wire-bonding of the chips.
The multi-chip module of the invention can be used to pack two or more chips in a stacked manner in the same package. It is a characteristic feature of the invention that the wire-bonding process for the second chip should be performed through a reverse wire-bonding technique, by which the outer ends of the bonding wires are first bonded to the substrate, and then the inner ends thereof are pulled up towards the bond pads of the first semiconductor chip and then stitch bonded to the bond pads. After that, an adhesive layer is coated to entirely wrap the part of the first set of bonding wires that is positioned above the first chip.